1. Field of the Invention
The present invention relates to instruction set computing. In one example, the techniques of the present invention provide mechanisms for allowing the implementing of complex parallel instructions in a processor core.
2. Description of the Prior Art
Typical processors largely fall into the Reduced Instruction Set Computing (RISC) or the Complex Instruction Set Computing (CISC) category. RISC processors generally execute one instruction per clock cycle. Instructions include adds, subtracts, compares, tests, etc. Instructions have a fairly uniform length and instruction sets are streamlined to contain only the most frequently used instructions. More involved operations are performed by breaking down operations into simpler instructions.
CISC processors typically execute slightly more complex, varying length instructions in multiple clock cycles. For example, instead of performing a simple comparison, a CISC instruction could compare a value against an upper bound as well as a lower bound. Instead of merely testing a condition, a CISC instruction can test, decrement, and branch in a single instruction.
Conventional RISC and CISC processors provide instructions that can be used to perform a variety of operations. However, using RISC or CISC processor to perform more involved operations such as digital signal processing, video processing, or cryptographic operations can be inefficient. Many operations involved in digital signal processing, video processing, and cryptography are redundant but involved operations that are highly suitable for implementation on specialized accelerators. A variety of Application Specific Integrated Circuits (ASICs) such as Digital Signal Processors, Video Accelerators, and Cryptography Accelerators are customized for performing specialized operations efficiently. Some of these accelerators are coupled to a processor using a system bus. However, separate accelerators introduce latency and other inefficiencies into a computer system.
Consequently, it is therefore desirable to provide improved methods and apparatus for improving performance of specialized operations. More specifically, it is desirable to provide improved mechanisms for implementing specialized operations on a system on a programmable chip or a system on a chip.